Publications

A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention

Published in Journal of Cryptographic Engineering (Springer), 2022

Hardware Trojans have emerged as a great threat to the trustability of modern electronic systems. A deployed electronic system with one or more undetected Hardware Trojan-infected components can cause grave harm, ranging from personal information loss to destruction of national infrastructure. The inherently surreptitious nature and bewildering variety of Hardware Trojans makes their detection an extremely challenging exercise. In this paper, we explore the state of the art of post-silicon testing techniques for Hardware Trojan detection, with our coverage including both physical measurement-based testing, as well as logic testing. We present systematic classification of Hardware Trojans and a taxonomy of detection techniques based on physical and logical testing, and describe these techniques in details, including their stand-out features and strengths and weaknesses. We conclude the paper with an evaluation of the current status of progress, and major directions of future research.

Recommended citation: R. Mukherjee, S. R. Rajendran, and R. S. Chakraborty, ‘A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention’, Journal of Cryptographic Engineering, vol. 12, no. 4, pp. 495–522, Nov. 2022. https://link.springer.com/article/10.1007/s13389-022-00295-w

Novel Hardware Trojan Attack on Activation Parameters of FPGA-based DNN Accelerators

Published in IEEE Embedded Systems Letters, 2022

Deep Neural Network (DNN) hardware accelerators are being deployed widely to accelerate the inference process. Security of such accelerators is a major challenge, especially when being deployed in safety-critical systems such as autonomous vehicles. In this paper, we present novel Hardware Trojan (HT) attacks on two DNN hardware accelerators, which modifies the activation parameters of the DNN in a FPGA-based accelerator implementation. The proposed HT is agnostic to the detailed architecture of the DNN. Experimental results demonstrate that the proposed HT is extremely stealthy, and when activated can result in significant degradation in inference accuracy.

Recommended citation: R. Mukherjee and R. S. Chakraborty, "Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators," in IEEE Embedded Systems Letters, vol. 14, no. 3, pp. 131-134, Sept. 2022, doi: 10.1109/LES.2022.3159541. https://ieeexplore.ieee.org/document/9734742

APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network

Published in Proceedings of the 2021 on Great Lakes Symposium on VLSI, 2021

Analysis of Physically Unclocnable Functions (PUFs) from a Boolean function perspective, and the efficient hardware implementation of such Boolean representations, can potentially lead to interesting insights about their behavior and robustness. Such a circuit implementation can also be a convenient substitute for the machine learning model of a PUF instance in PUF-based security protocols. In this paper, we present APUF-BN, a novel computer-aided design (CAD) framework to efficiently generate a combinational circuit representation of an Arbiter PUF (APUF) instance, which accurately mimics its input-output behavior. This representation is derived from an optimized fully-connected Binarized Neural Network (BNN) model of the APUF. Our fully-automated CAD framework takes challenge-response pairs (CRPs) of an APUF instance as input, and generates Verilog description corresponding to the optimized combinational circuit representation as output. The optimized Boolean logic representation achieves more than 24% reduction in area overhead compared to the unoptimized BNN representation, while achieving close to 98% modeling accuracy. We also validate the derived combinational circuit representation on Xilinx Artix-7 FPGA platform.

Recommended citation: Santikellur, P., Mukherjee, R., & Chakraborty, R. S. (2021). APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network. Proceedings of the 2021 on Great Lakes Symposium on VLSI, 89–94. https://dl.acm.org/doi/abs/10.1145/3453688.3461484

Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure

Published in Journal of Hardware and Systems Security (Springer), 2020

Over the past decades, there has been an exponential growth in the number of connected devices, often without well-thought out security mechanisms in place for the relevant network standards and protocols. As a result, security loopholes have been discovered and widely exploited for these vulnerable connected devices, often with devastating consequences. As a countermeasure to these attacks, subsequently some of these original network standards have been enhanced with addition of security features, e.g., the original insecure Ethernet protocol (IEEE 802.3) was supplemented by the IEEE 802.1AE Media Access Control Security (MACSec) standard. In this paper, we present a network packet redirection attack on reconfigurable network devices, specifically a MACSec-enabled NetFPGA-SUME based Ethernet switch, as well as on a NetFPGA-SUME based IPv4 router, by means of Hardware Trojan (HT) insertion. Our HT design is probabilistic in its functionality, with multi-level trigger mechanism. In the MAC layer attack, an activated HT redirects a frame to an incorrect port leading to possible eavesdropping by a malicious attacker as well as denial-of-service, while in the network layer attack, upon activation it forwards all IP packets through a sub-optimal router port causing a denial-of-service attack on the receiver. The proposed HT evades most state-of-the-art HT detection schemes, while having very low resource footprint. We present the complete architecture, detailed description of the mode of operation, and implementation of the HT, with promising experimental results.

Recommended citation: Mukherjee, R., Govindan, V., Koteshwara, S., Das, A., Parhi, K. K., & Chakraborty, R. S. (2020). Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure. Journal of Hardware and Systems Security, 4(4), 343–360. https://link.springer.com/article/10.1007/s41635-020-00107-9

SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection

Published in Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security, 2020

Hardware Trojans have emerged as great threat to the trustability of modern electronic systems. A deployed electronic system with one or more undetected Hardware Trojan-infected components can cause grave harm, ranging from personal information loss to destruction of national infrastructure. The inherently surreptitious nature and bewildering variety of Hardware Trojans makes their detection an extremely challenging exercise. In this paper, we explore the state-of-the-art of non-destructive testing for Hardware Trojan detection, with our coverage including both physical measurement based testing, as well as logic testing. We present systematic classification of Hardware Trojans and their detection techniques, and describe these techniques in details, including their stand-out features and strengths and weaknesses. We conclude the paper with an evaluation of the current status of progress, and major directions of future research.

Recommended citation: Rajendran, S. R., Mukherjee, R., & Chakraborty, R. S. (2020). SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection. Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security, 103–116. https://dl.acm.org/doi/10.1145/3411504.3421211

Rijoy Mukherjee